The S-parameters are only a good characterization for small
signal circuits. Power amplifiers are very nonlinear and the S-parameters
will depend on power level. Despite this S-parameters measured at
the input port at the power level also used in the application
are a very good starting point for the design of the input
matching network. Even more critical is the output of an RF power
amplifier. Power match based on small-signal S-parameters will
result in highest small-signal power gain but for RF power
amplifiers the output power itself and the power efficiency are
much more important. So the question is: What impedance should be
applied at the amplifier output to get a given output power with
best efficiency? Many people are using an impedance tuner to
search for the best match by hand. This will lead to a complete
different design procedure then typical used in small-signal
amplifiers! Also here with some theory a faster way is possible.

Let us consider a concrete design problem:

Design a matching network for a DECT power amplifier. The 1.9GHz
digital European cordless phone standard allows 24dBm (250mW) at
the antenna. In reality some loss occurs in the TX filter and
antenna switch, so the PA should deliver app. 26dBm. When we want
to use a balanced PA (with push-pull output stage) like the
Infineon PMB6819 (low cost Silicon device with integrated system
functions), we need a good match and a BALUN.

The output power depends also on supply voltage (due to P=V_{rms}ē/R_{L})
and best efficiency (app. 45%) can be expected when the PA is
deep in the compression. This is no problem because DECT uses
GFSK modulation with constant envellope. The datasheet recommends
a supply voltage of 2.4V (2 NiCd cells), so we can calculate the
load impedance R_{L} using the AdLab
tool ANPASS (assume that the transistor saturation voltage is app.
0.2V).

Figure 1 : Calculating R_{Lopt} via ANPASS

The result is a reell value for the impedance (20W, so 10W for
each side) which is not truly realistic with real world
transistors and finite package inductances. So ANPASS delivers
the correct value for an idealized PA in class-A operation (hints
avalable on bubble help). For class-B operation used in the PMB6819
a higher value of R_{Lopt} is a bit better for higher
efficiency (say 11W). Using CSERPAR we
can start with the corrected value as the generator impedance and
we can add the transistor output capacitance (app. 3pF) and the
pin inductance (app. 0.8nH and a small package capacitance) by
hand.

Figure 2 : PA modeling in CSERPAR and the matching network to 35W. Note: The end capacitor has a series
inductances of 0.7nH as a typical SMD component.

What we need now is a match from the transistor output to the
BALUN. A BALUN transforms the differential PMB6819 output to a
single-ended output (which is normally 50W).
A BALUN can be designed using ANPASS. One open question ist the
intermediate BALUN input impedance. Itīs a good idea to take an
intermediate impedance value (say 35W)
so that the match is distributed over the first matching network
and the BALUN. This often gives the largest bandwidth and low
tolerances.

Figure 3 : LC BALUN design using ANPASS

The resulting circuit is very close to what is shown in Infineonīs
PMB6819 data sheet. Of course in reality some tweaking is always
needed in 1.9GHz circuits due to component parasitics and
modeling inaccuracies. Also the impedance at the harmonic
frequency is noit unimportant due to large signal operation. This
behavior is known as harmonic matching, but it is not easy to get
advantage from this behavior at a GHz power amplifier.

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Copyright Đ 2001 Stephan Weber. All rights reserved.

Stand: April 22, 2001.